INTEGRATION GUIDE
How NeuraEdge connects to your SoC.
Every interface parameter, memory specification, and power domain is documented in the delivery package. Below is a public summary of the integration model so you can evaluate fit before signing an NDA.
TOP-LEVEL INTERFACE
I/O boundary definition — neuraedge_top_2x2.
| Interface | Type | Width | Notes |
|---|---|---|---|
| clk | Input | 1-bit | Single clock domain |
| rst_n | Input | 1-bit | Active-low async reset |
| AXI-Lite CSR | Slave | 32-bit | Config / status registers |
| DMA AXI | Master | 64-bit | Memory access (LPDDR4 in v2.0) |
| JTAG | IEEE 1149.1 | 4-pin | Debug + scan access |
| Scan chains | Input/Output | 80 | Test mode |
| Power domains | UPF 3.0 | 5 | 1 AO + 4 tile gating |
| IRQ | Output | 1-bit | Interrupt to host CPU |
MEMORY SUBSYSTEM
Memory integration requirements for TSMC 40nm tape-out.
4 unique SRAM macro types required. Full JSON specifications for each macro included in v2.0 delivery package.
| Macro | Instances | Spec | Source |
|---|---|---|---|
| PE Weight SRAMs | 64 | 8-bit × 64-deep, single-port | TSMC memory compiler or Faraday FCLLM |
| Firmware IRAM | 1 | 32-bit × 8192-deep, 2R1W | TSMC memory compiler |
| Firmware DRAM | 1 | 32-bit × 4096-deep, 1R1W | TSMC memory compiler |
| Router FIFO SRAMs | 80 | 64-bit × 4-deep, single-port | TSMC memory compiler |
CLOCK DOMAIN ARCHITECTURE
4 clock domains. Single main clock. Per-PE gating.
| Domain | Source | Target freq (40nm) | Notes |
|---|---|---|---|
| clk (main) | External PLL | 200–400 MHz | All compute logic |
| jtag_tck | JTAG interface | 10–50 MHz | Debug / test access |
| scan_tck | Test mode | At-speed | OPCG-generated |
| PE gated clks | ICG (per PE) | Derived from clk | 64 ICG instances, per-PE |
CDC paths: 42 identified, 11 require synchronizers.
Synchronizer library included in delivery package.
Commercial CDC sign-off report: v1.1 commitment.
POWER DOMAIN ARCHITECTURE
5 domains. 8 power states. Tile-level power gating.
UPF 3.0 source included in delivery package. Power switch cell sizing: TSMC 40nm HSW_* cells required (specification in v2.0 delivery package).
| Domain | Type | v1.0 Voltage | v2.0 TSMC 40nm |
|---|---|---|---|
| Always-On (AO) | Permanent | 1.8V | 1.1V (core) / 1.8V (IO) |
| Tile 0 | Power-gated | 1.8V | 1.1V |
| Tile 1 | Power-gated | 1.8V | 1.1V |
| Tile 2 | Power-gated | 1.8V | 1.1V |
| Tile 3 | Power-gated | 1.8V | 1.1V |
8 power states: ALL_ON through ALL_TILES_OFF
THIRD-PARTY COMPONENT DISCLOSURE
Ibex RV32IMC Core.
Source: LowRISC / lowRISC contributors
License: Apache 2.0 (open source, unrestricted commercial use)
Files: 30 RTL files, 19,889 lines
Role: On-chip control processor for NeuraEdge firmware execution, CSR access, and interrupt handling
Integration: Full source included in delivery package. No additional licensing required.
INTEGRATION TIMELINE
5 steps to tape-out ready.
RTL ingestion
Drop 91 RTL files into your design flow. Run lint. Verify with your preferred simulator.
Constraint setup
Apply SDC timing constraints and UPF power intent from the delivery package.
SoC integration
Connect APB control bus, data interface, interrupt line, and reset. Estimated 2–4 weeks for experienced team.
Verification
Run provided testbenches (249 tests). Add your own SoC-level tests. GLS at target PVT corners.
Synthesis & place-and-route
Synthesize with your PDK. Place-and-route with your implementation flow. Signoff at target node.
Integration timeline assumes an experienced SoC team with existing APB infrastructure. First-pass integration on a new platform: estimated 8–12 weeks to GLS verification.
Full integration guide included in delivery.
The delivery package includes a complete integration guide with pin-out diagrams, timing diagrams, constraint templates, and a step-by-step walkthrough for your implementation flow.